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signal processing technologies, inc. 4755 forge road, colorado springs, colorado 80907, usa phone: 719-528-2300 fax: 719-528-2370 web site: http://www.spt.com e-mail: sales@spt.com spt5320 12-bit, 160 mwps d/a converter advance information features ? 12-bit, 160 mwps digital-to-analog converter 1.0 lsb inl; 0.5 lsb dnl +2.7 v to +5.5 v operation for digital supplies high wideband spurious free dynamic range low glitch impulse 5 pv-s low power: 100 mw @ +3.0 v digital supply internal voltage reference powerdown mode applications broadband modems wireless local loops cellular and pcs basestations head-end broadcast video transmission systems professional broadcast video equipment communications test equipment direct digital synthesis description the spt5320 is a 12-bit, 160 mwps digital-to-analog converter designed primarily for rf communications and instrumentation applications. it provides excellent spurious performance operation at the lowest possible cost. the digital power supply can range from +2.7 v to +5.5 v. the spt5320 operates at an industrial temperature range of ?40 c to +85 c and is available in 28-lead soic or ssop-equivalent packages. block diagram

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spt 2 8/24/00 spt5320 absolute maximum ratings (beyond which damage may occur) 1 25 c note 1: operation at any absolute maximum rating is not implied. see electrical specifications for proper nominal applied condit ions in typical applications. supply voltages av dd .................................................... ?0.3 v to +6.5 v dv dd ................................................... ?0.3 v to +6.5 v agnd, dgnd, rgnd ......................... ?0.3 v to +0.3 v agnd ? dgnd .............................................. 300 mv input voltages digital inputs ............................. ?0.3 v to dv dd + 0.3 v v ref , r set ................................ ?0.3 v to av dd + 0.3 v comp ...................................... ?0.3 v to av dd + 0.3 v output i outa , i outb current ............................................ 15 ma i outa , i outb voltage ...................... ?1.0 to av dd + 0.3 v temperature operating temperature ........................... ?40 to +85 c junction temperature ...................................... +175 c lead temperature, (soldering 10 seconds) ...... +300 c storage temperature ............................ ?65 to +150 c electrical specifications t a =t min to t max , av dd =dv dd =+5.0 v, unless otherwise specified. test test spt5320 parameters conditions level min typ max units dc performance resolution 12 bits differential linearity 25 c 0.5 lsb differential linearity full temp. 1.0 lsb integral linearity 25 c 1.0 lsb integral linearity full temp. 2.0 lsb offset error 0.025 % fs gain error (without internal reference) 2 10 % fs gain error (with internal reference) 1 10 % fs full-scale output current 20.48 ma output compliance voltage ?1.0 +1.25 v equivalent output resistance >100 k ? gain error tempco tbd ppm/c zero-scale offset error 0.025 % fs output capacitance 5pf offset drift tbd ppm fs/c gain drift (without internal reference) 50 ppm fs/c gain drift (with internal reference) 100 ppm fs/c dynamic performance maximum output update rate 160 mwps output settling time (to 0.1%) 25 35 ns output propagation delay tbd ns glitch impulse 5pv-s output rise time (10% to 90%) tbd ns output fall time (10% to 90%) tbd ns output noise (i outfs = 10 ma) 25 50 pa/ hz spurious free dynamic range to nyquist ? clk = 50 mhz; ? out = 20 mhz 67 dbc ? clk = 100 mhz; ? out = 20 mhz 67 dbc ? clk = 160 mhz; ? out = 20 mhz 63 dbc spurious free dynamic range within a window ? clk = 50 mhz; ? out = 5 mhz; 2 mhz span 86 dbc ? clk = 100 mhz; ? out = 5 mhz; 4 mhz span 86 dbc multitone power ratio (8 tones at 110 khz spacing) ? clk = 20 mhz; ? out = 2.00 to 2.99 mhz 75 dbc
spt 3 8/24/00 spt5320 test level codes all electrical characteristics are subject to the following conditions: all parameters having min/max specifi- cations are guaranteed. the test level column indicates the specific device testing actually performed during pro- duction and quality assurance inspec- tion. any blank section in the data column indicates that the specification is not tested at the specified condition. test level test procedure i 100% production tested at the specified temperature. ii 100% production tested at t a = +25 c, and sample tested at the specified temperatures. iii qa sample tested only at the specified temperatures. iv parameter is guaranteed (but not tested) by design and characteriza- tion data. v parameter is a typical value for information purposes only. vi 100% production tested at t a = +25 c. parameter is guaranteed over specified temperature range. electrical specifications t a =t min to t max , av dd =dv dd =+5.0 v, unless otherwise specified. test test spt5320 parameters conditions level min typ max units power supply requirements analog supply voltage av dd 4.5 5.5 v digital supply voltage dv dd 2.7 5.5 v analog supply current tbd tbd ma digital supply current tbd tbd ma supply current sleep mode tbd 5 ma power dissipation at +3 v supplies and 10 ma current output 100 mw at +5 v supplies and 10 ma current output 300 mw power supply rejection ratio (av dd ) 0.02 0.2 %fs/v power supply rejection ratio (dv dd ) 0.002 0.025 %fs/v reference reference voltage 1.20 v reference output current tbd reference input compliance range 0.1 1.25 v small signal bandwidth tbd mhz reference voltage drift 50 ppm/c digital inputs logic ?1? voltage (dv dd = +3 v) 2.1 v logic ?0? voltage (dv dd = +3 v) 0.9 v logic ?1? voltage (dv dd = +5 v) 3.5 v logic ?0? voltage (dv dd = +5 v) 1.3 v logic ?1? current ?10 +10 a logic ?0? current ?10 +10 a input capacitance 35pf input setup time ? t s 2<1 ns input hold time ? t h 2<1 ns latch pulse width ? t lpw tbd ns
spt 4 8/24/00 spt5320 pin functions name function analog outputs i outa dac current output. i outb complementary current output. digital inputs d0?d11 digital inputs (d0 is the lsb) sleep sleep mode pin. active high. contains active pull- down resistor. clk clock input pin. data is latched on the rising edge. reference & compensation rgnd reference ground when using internal 1.2 v reference. connect to av dd to disable internal reference. v ref reference input/output. serves as an input when internal reference is disabled. serves as a 1.2 v reference output when internal reference is enabled. requires a 0.1 f capacitor tied to agnd when internal reference is enabled. r set full-scale current output adjustment. comp internal bias node for switch driver circuitry. use 0.1 f capacitor tied to agnd. power agnd analog supply return. dgnd digital supply return. av dd analog +4.5 to +5.5 v supply. dv dd digital +2.7 to +5.5 v supply. n/c no connect. signal processing technologies, inc. reserves the right to change products and specifications without notice. permission is her eby expressly granted to copy this literature for informational purposes only. copying this material for any other use is strictly prohibited. warning ? life support applications policy ? spt products should not be used within life support systems without the specific written consent of spt. a life support system is a product or system intended to support or sustain life which, if it fails, can be reasonably expected to result in significant personal injury or death. signal processing technologies believes that ultrasonic cleaning of its products may damage the wire bonding, leading to device failure. it is therefore not recommended, and exposure of a device to such a process will void the product warranty. ordering information part number temperature range package SPT5320SIS ?40 c to +85 c 28l soic spt5320sir ?40 c to +85 c 28l ssop equivalent pin assignments # / 2 3 4 5 6 7 8 #% ## #/ #2 #3 /7 /6 /5 /4 /3 /2 // /# /% #8 #7 #6 #5 #4 ## #% 8 7 6 5 4 3 2 / # % ,9 ,9 0, ,9 & ! ' ! ' 0, ,9 0,

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